1. Field of the Invention
The present invention relates to a power supply voltage controlling circuit and controlling method for a subthreshold digital CMOS circuit. In particular, the present invention relates to a power supply voltage controlling circuit and controlling method for correcting an on-chip delay variation of a subthreshold digital CMOS circuit.
2. Description of the Related Art
Recently, it is required to remarkably reduce power consumption of LSIs due to emergence of numbers of micro-systems such as medical implanted devices and sensor devices. Up to now, the power consumption of CMOS circuits has been reduced by miniaturization of devices and reduction in the power supply voltage. In particular, the reduction in the power supply voltage is regarded to be an extremely effective technique for low power consumption operation since an operating power is proportional to a square of the power supply voltage.
Namely, a subthreshold CMOS circuit, in which a power supply voltage of the CMOS circuit is set to a voltage equal to or smaller than a threshold voltage of a transistor (for example, the threshold value is 0.35 V, and changes depending on a manufacturing process), leads to low power, and is regarded to be useful in applications having severe power constraints. For example, in the case of a very low power smart sensor LSI as shown in FIG. 1, a circuit is configured to include a sensor and a mixed signal circuit of analog and digital circuit blocks. By operating this circuit block in a subthreshold region, it is possible to achieve a lower power. A patent document related to the present invention is as follows:    Patent Document 1: Japanese patent laid-open publication No. JP-2007-036934-A.
However, in the CMOS circuit operating in the subthreshold region and including inverters each configured to include a pMOSFET and an nMOSFET, the threshold voltages of the MOSFETs fluctuate due to a temperature change and a manufacturing process variation. This leads to such a problem as significant fluctuations in a current-voltage characteristic. The fluctuation in the current-voltage characteristic exerts influences on the delay time, or an operating time of the CMOS circuit. In particular, the current in the subthreshold region fluctuates exponentially with respect to the threshold voltage, and therefore, the delay time also fluctuates following an exponential function. As a result, the subthreshold CMOS circuit has a delay variation larger than that of the CMOS circuit predicated on a strong inversion region, and this leads to such a problem that processings do not end within a preset delay constraint. As described above, in the subthreshold CMOS circuit, a transistor characteristic fluctuates due to the fluctuation in the threshold voltage, and this leads to fluctuation in the current and fluctuation in an operating characteristic of the subthreshold CMOS circuit.
As described above, the operating characteristic of the subthreshold CMOS circuit fluctuates due to the influences of the manufacturing process and a temperature change. However, according to the prior art, it is difficult to predict or guarantee the operating characteristic of the subthreshold CMOS circuit due to the fluctuation in the threshold voltage caused by the manufacturing process and the temperature change. Therefore, it is required to perform temperature compensation and process variation correction by circuit design architecture.
According to the prior art, there have been known techniques for reducing the influences of the fluctuation in the threshold voltage so as to secure stability of the circuit operation by a method for controlling the power supply voltage of the subthreshold CMOS circuit by using two types of constant voltages or by a method for changing a clock frequency. However, these techniques cannot be regarded to be essential improvements in the variation since the voltage and the clock used are not provided based on causes of the variation.
In addition, there have been known a technique in which the variation caused by the process variation is improved by short-circuiting input and output of the subthreshold CMOS circuit and changing a substrate bias of a transistor by using a signal (See the Patent Document 1, for example) of the circuit. However, it has been known that an effect of the improvement in the variation with respect to the substrate bias is small since a control range of the substrate voltage is narrow. In addition, there is such a problem that consumption current is increased by a leakage current due to a forward bias.
As described above, the subthreshold CMOS circuit can achieve low power consumption. On the other hand, there is such a problem that the delay time of the subthreshold CMOS circuit is largely influenced by the fluctuation in the threshold voltage of the MOSFET, which changes according to the temperature change and the manufacturing process.